1. Field of the Invention
This invention relates to magnetic memory cells and, more particularly, to a system and method for improving the write selectivity of individual memory cells in a magnetic random access memory (MRAM) array.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
A non-volatile memory circuit maintains stored information even when electricity is removed from the circuit. Recently, advancements in the use of magneto-resistive materials have revolutionized the development of non-volatile memory circuits with the introduction of magnetic random access memory (MRAM). MRAM circuits advantageously exploit the electromagnetic properties of magneto-resistive materials to set and maintain information stored within individual memory cells of the circuit. In particular, MRAM circuits utilize magnetization direction to store information within a memory cell, and differential resistance measurements to read information from the memory cell. In other words, information is stored within an MRAM cell as a magnetic bit, the state of which is indicated by the orientation of magnetization within one layer of the memory cell relative to another layer of the memory cell. In addition, a differential resistance can be obtained from differences in the magnetization directions between layers of the memory cell. Such a differential resistance can be used to read the magnetic state of the bit stored in the MRAM cell.
An MRAM cell typically includes a plurality of layers with at least two magnetic layers separated by a nonmagnetic layer, and therefore, is sometimes referred to as a magnetic stack. A lower magnetic layer (e.g., a pinned magnetic layer) of the magnetic stack is usually fixed in a predefined magnetic direction to be used as a reference direction. To store information, however, the magnetic direction of an upper magnetic layer (e.g., a storage layer or a free magnetic layer), which is separated from the lower magnetic layer by a nonmagnetic layer, can be manipulated into a direction that is parallel or anti-parallel to the magnetic direction of the lower magnetic layer. Note that the term anti-parallel is used herein to describe a magnetic direction that is oriented 180xc2x0 from the reference magnetic direction of the lower magnetic layer.
In general, a bit of information may be written to an MRAM cell by applying current that induces a magnetic field external to the cell. Such an external magnetic field may then force a majority of the internal magnetic field vectors within the free magnetic layer to align in a direction, either parallel or anti-parallel, relative to the magnetic direction of the pinned magnetic layer. Thus, the magnetic state of the stored bit is determined by the variable magnetic direction within the free magnetic layer. Once the bit is stored, however, the current may be discontinued without losing or altering the magnetic state of the stored bit.
In one example, a bit may be written to the free magnetic layer of an MRAM cell as a logic xe2x80x9c0xe2x80x9d (i.e., logic low) value when the magnetic direction of the free magnetic layer is substantially parallel to the magnetic direction of the pinned magnetic layer. In another example, a bit may be written to the free magnetic layer of an MRAM cell as a logic xe2x80x9c1xe2x80x9d (i.e., logic high) value when the magnetic direction of the free magnetic layer is substantially anti-parallel to the magnetic direction of the pinned magnetic layer. In either example, the stored bit may be read from the MRAM cell by measuring the resistance between the free and pinned magnetic layers, such that a logic 1 value is determined by a relatively higher resistance than a logic 0 value.
In addition, an MRAM cell typically includes an easy axis and a hard axis of magnetization, both of which are oriented along a single plane in directions perpendicular to one another. Note that the terms easy axis and hard axis of magnetization are used herein to describe the inherent tendency of the magnetization within the free magnetic layer to align along one axis versus another axis, at times when substantially no external magnetic field is present. In particular, the previously defined parallel or uni-parallel-anti-parallel directions of magnetization are typically oriented along the easy axis of magnetization. Such an orientation along the easy axis usually permits the stored information to be non-volatile. In other words, the magnetization within the free magnetic layer (inc., stored information) may be retained along either the parallel and anti-parallel orientation of the easy axis even when power to the memory cell is removed.
As will be discussed in more detail below, the easy axis of magnetization is usually an inherent result of the shape of the MRAM cell. Thus, the easy axis of magnetization is typically arranged along the length of the MRAM cell, and is sometimes referred to as the long, or longitudinal axis of magnetization. The magnetic state of the MRAM cell is usually defined by the magnetic direction along the easy axis of magnetization. The magnetic hard axis, however, is typically arranged along the width of the MRAM cell, and is sometimes referred to as the short, or transverse axis of magnetization. Since an external magnetic field may be needed to orient the magnetization within the free magnetic layer along the hard axis, the magnetic state of the MRAM cell is not typically stored along the hard axis.
An MRAM circuit typically includes a plurality of bit lines and digit lines, such that the plurality of bit lines is substantially perpendicular to the plurality of digit lines. An MRAM circuit also includes a plurality of MRAM cells, such as those described above, where each of the plurality of MRAM cells is approximately arranged at intersecting regions between individual bit lines and digit lines. In this manner, when current is simultaneously applied along a particular bit line and a particular digit line, the applied current may induce an external magnetic field large enough to switch the magnetization of an individual memory cell. Such an individual memory cell may herein be referred to as a selected memory cell, or the memory cell intentionally targeted for a writing procedure.
During the writing procedure, the multitude of memory cells arranged along the selected bit line and the selected digit line will sense an amount of current typically less than the amount of current sensed by the selected memory cell. Such memory cells are herein referred to as half selected cells, or disturbed cells. Even though less current is applied to these disturbed cells, fabrication process variations may allow a false bit to be unintentionally written to one or more of the disturbed cells. The writing of false bits, however, is undesirable and indicates failure of the memory device to store accurate information. Though all memory cells within an MRAM circuit are generally fabricated at the same time, variations in the fabrication process may produce variations in shape, size, and/or the presence of defects within individual memory cells. It may be these variations within individual memory cells that are typically responsible for the occurrence of false bits.
As such, a particular MRAM cell shape (e.g., an elliptically-shaped memory cell) may store inaccurate information due to its sensitivity to variations in shape, size, and defects. In fact, the variations may be so large that information can be accidentally stored to one or more unselected memory cells (i.e., cells not arranged along the selected bit line or digit line), which exhibit unusually lower switching fields than expected. Sensitivity to variations in shape and size may also disadvantageously reduce the current margin between selected and disturbed cells, thereby reducing the write selectivity between MRAM cells. In other words, the relative difference (i.e., current margin) between the amount of current responsible for switching the magnetization of a disturbed cell and the amount of current needed to switch the magnetization of a selected cell (i.e., the write selectivity) may be reduced as a result of the variations within individual memory cells.
Therefore, it would be advantageous to provide an MRAM cell having a configuration that is substantially insensitive to variations in shape, size, and the presence of defects. Such a memory cell configuration may advantageously increase the write selectivity between select and disturb cells over other cell configurations. In addition, it would be beneficial to provide a method, which not only reduces the current margin between individual memory cells, but also reduces the overall amount of current required during a writing procedure.
The problems outlined above may be in large part addressed by a memory cell and method for improving the write selectivity of individual memory cells in an MRAM array. In particular, the above problems may be addressed by a memory cell having at least one magnetic layer with a shape that is substantially asymmetrical about at least one axis of the magnetic layer. Such asymmetry may advantageously increase the write selectivity of individual cells within an MRAM array by reducing and/or eliminating the effects due to variations in the fabrication process. Such process variations may result in, for example, variations in shape and size of the magnetic layer, as well as the presence of defects on/within the magnetic layer. In addition, an asymmetrical memory shape tends to induce a relatively consistent equilibrium vector state, due to its insensitivity to variations in shape and size. Such a consistent equilibrium state allows a single switching mechanism to set the magnetic direction of the cell. As a result, the variation in current used to write an asymmetrical memory cell may be less than the current used to write a symmetrical memory cell. Furthermore, a method is provided herein for programming a memory cell, in which the amount of current needed during a writing procedure is advantageously reduced relative to the amount of current needed in conventional writing procedures. In this manner, the asymmetrical memory cell and method produces a storage medium having overall power requirements less than those associated with symmetrical memory cells.
As stated above, a memory cell having at least one magnetic layer with a shape that is substantially asymmetrical about at least one axis of the magnetic layer is provided herein. In some cases, the memory cell may include a plurality of layers having shapes substantially similar to the asymmetrical shape of the magnetic layer. In such a case, the plurality of layers may include a portion of the layers within a memory cell stack. In other cases, however, the plurality of layers may include all of the layers within a memory cell stack. In one embodiment, the memory cell has an asymmetric configuration about a first axis (e.g., the magnetic easy axis direction). More specifically, one or more layers of the memory cell may have an asymmetric configuration about a first axis of the memory cell. In some cases, the first axis may be arranged along the length, or an elongated dimension of the memory cell.
In an alternative embodiment, the memory cell may have an asymmetric configuration about a second direction (e.g., the magnetic hard axis direction), such that the second direction is perpendicular to the first direction. In some cases, such a second direction may be arranged along the width, or a shortened dimension of the memory cell. In either case, a memory cell is provided having at least one magnetic layer with a shape that is substantially asymmetrical about at least one dimension of the magnetic layer. In yet another embodiment, the memory cell may have an asymmetric configuration about both the first and second directions. In this manner, the shape of the magnetic layer may be asymmetrical along an elongated dimension of the memory cell in addition to a dimension perpendicular to the elongated dimension.
In any case, the shape of the asymmetric memory cell may include a curved portion along at least one side of the memory cell, in some embodiments. As such, the curved portion may be aligned with the axis (or axes) in which the asymmetry resides. For example, the asymmetric configuration (or shape) of the memory cell may include a curved portion along at least one side of the memory cell, which is substantially aligned with the elongated dimension of the memory cell. Alternatively, the asymmetric configuration of the memory cell may include a curved portion, which is substantially aligned with the shortened dimension of the memory cell. Such asymmetry (whether about the easy axis, hard axis, or both axes) advantageously decreases the sensitivity of the memory cell to defects, as well as to variations in shape and size, since the shape of the memory cell (i.e., dot) sets the reversal of magnetization.
In some embodiments, the magnetic memory cell may include a magnetic layer with a perimeter having a larger curvature along one side of the perimeter than an opposing side of the perimeter. In such an embodiment, the opposing side of the perimeter may have a curvature, which is concave or convex, or alternatively, the opposing side may be substantially straight. In some cases, the one side of the perimeter may include a curved portion having a different radial length than other curved portions arranged along the one side of the perimeter. In other cases, however, the one side of the perimeter may include a curved portion having a single radial length. In any case, the one side and the opposing side of the perimeter may be arranged along the length, or along an elongated dimension of the magnetic layer. Alternatively, the one side and the opposing side of the perimeter may be arranged along the width, or along a shortened dimension of the magnetic layer.
A method for programming a magnetic memory cell is also provided herein. Such a method may be used to reduce the amount of current needed to write information to a memory cell by enforcing a destabilizing magnetic vector state (or magnetic vector field pattern) within the memory cell prior to setting the magnetic direction of the cell. In particular, the method may include destabilizing a magnetic vector state of a selected memory cell with a first magnetic field by applying current to a first conductive line. During such a step, the first magnetic field may be along a direction that is transverse to an overall direction of the magnetic vector field pattern of the selected memory cell. Such an overall direction may be a direction associated with a majority of the magnetic vectors arranged within the memory cell.
In one example, the current applied to the first conductive line during the step of destabilization may be along a direction of the first conductive line that is substantially aligned with the direction of the majority of magnetic vectors arranged within the memory cell. In an alternative example, the current may be applied to the first conductive line along a direction substantially opposite to the direction of the majority of magnetic vectors. Such an alternative example, however, would result in a higher switching field. In either embodiment, the method may further include setting a magnetic direction (or magnetic state) of a selected memory cell with a second magnetic field induced by a current applied to the first conductive line and a current applied to a second conductive line. As such, the second magnetic field is a combined magnetic field, which is induced by the currents applied to both the first and second conductive lines. After setting the magnetic state of the memory cell, the method may include stabilizing the magnetic vector field pattern of the selected memory cell along the set magnetic direction with a magnetic field induced by the current applied to the second conductive line. During such a stabilizing step, the current applied to (the first conductive line may be reduced, or alternatively, may be discontinued altogether.
In some cases, the magnetic memory cell may also be aligned with other memory cells in an array configuration. As such, the step of destabilizing may also include destabilizing the magnetic vector states of the other memory cells spaced above the first conductive line. In such a case, the method may include re-stabilizing the magnetic vector states of the other memory cells subsequent to the step of setting the magnetic direction of the selected memory cell. Such a re-stabilizing step may include discontinuing the current applied to the first conductive line. In another embodiment, the method may not discontinue the current applied to the first conductive line completely, but instead, may reduce the current applied to the first conductive line until the induced magnetic field decreases to a point in which the magnetic vector states of the memory cells are re-stabilized. In either embodiment, the step of re-stabilizing may include discontinuing (or reducing) the current applied to the first conductive line prior to discontinuing the current applied to the second conductive line. Alternatively, the method may include discontinuing (or reducing) the current applied to the first conductive line at approximately the same time as discontinuing the current applied to the second conductive line. Thus, the magnetic state of the memory cell may be stabilized and maintained even after current is completely removed from the vicinity of the memory cell. As such, the asymmetrical MRAM cell and method produces a non-volatile storage medium having overall power requirements less than those associated with symmetrical memory cells.
A method for forming a magnetic field is also provided herein. Such a method may include forming a portion of the magnetic field in an arcuate pattern along a first periphery, while simultaneously forming another portion of the magnetic field in a linear pattern along an opposed, second periphery. After the forming step, the method may include an additional forming step in which another portion of the magnetic field is formed in an arcuate pattern partially along both the first and second peripheries. Next, the method may include reversing a magnetic direction of the arcuate pattern is formed along both the first and second peripheries. After the reversing step, the method may include altering the arcuate pattern formed along the first and second peripheries to form a different pattern. In this manner, the different pattern may include another arcuate pattern along the first periphery and another substantially linear pattern along the second periphery.
Incorporated by reference is a twenty-one (21) page appendix describing further the details of the present embodiments.